module top(input clk1,
           input clk2,
           input select,
           input rst_n,
           output clk_out);
    
    reg out1;
    reg out2;
    reg out1_r;
    reg out2_r;
    assign clk_out = (out1_r&clk1)|(out2_r&clk2);
    always@(posedge clk1 or negedge rst_n)
    begin
        if (!rst_n)
            out1 <= 1'b0;
        else
            out1 <= (~out2_r)&select;
    end
    always@(negedge clk1 or negedge rst_n)
    begin
        if (!rst_n)
            out1_r <= 1'b0;
        else
            out1_r <= out1;
    end
    always@(posedge clk2 or negedge rst_n)
    begin
        if (!rst_n)
            out2 <= 1;
        else
            out2 <= (~out1_r)&(~select);
    end
    always@(negedge clk2 or negedge rst_n)
    begin
        if (!rst_n)
            out2_r <= 1'b0;
        else
            out2_r <= out2;
    end
endmodule
